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Beetle Bailey for Thu, 24 Sep 2026

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Beetle Bailey – Thu, September 24, 2026

By Mort Walker

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Source: Beetle Bailey

Bringing Up Father for Wed, 23 Sep 2026

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Bringing Up Father – Wed, September 23, 2026

By George McManus

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Source: Bringing Up Father

Show HN: An atlas of system designs with interactive architecture diagrams

02

One copy or many

Speed and availability, paid for in consistency

Replicas and caches put data closer to readers and survive failures, but every extra copy can lag behind the source of truth. The real question is how stale a read the product can tolerate.

One copyAlways consistentBottleneck, single point of failure
Many copiesFast, resilient readsReplication lag, conflicts


Source: Hacker News

Show HN: Conway's Game of Life in boot sector

BootLife

Conway’s Game of Life running directly from a 512-byte x86 boot sector, using VGA memory as the simulation grid.

Usage • Why • Contributing • Author

Size
Platform
Assembler
License

Patreon
Buy Me a Coffee

BootLife running in QEMU

Usage

To build and run bootlife you need:

Use the following commands to run it:

nasm -f bin -o life.img life.asm

qemu-system-i386 -drive file=life.img,format=raw,if=floppy

Or just:

make run

Why

Just for fun 💾

Contributing

Bug reports and pull requests are welcome – see CONTRIBUTING.md.

Author

0xAX


Source: Hacker News

When the Debugger Lies

I’ve spent the last few weeks working with the security architecture of the
nRF54L series from Nordic
Semiconductor
(in case you missed it, I recently
joined Nordic
!).
While doing so, I have engaged my typical low-level learning technique of
eschewing writing firmware for manually poking at registers using the debugger.
A few nights ago I found myself observing unexpected values in memory when
working with the key management unit. It turned out to be a familiar issue, but
one that requires an understanding of the internal system on chip (SoC)
components, and how the debugger interacts with them, to diagnose.

For a bit of background, the nRF54L series has a fairly advanced set of security
capabilities, headlined by Arm
TrustZone
support in
the Cortex-M33
core
, a
CRACEN cryptographic
accelerator
,
and a Key Management Unit
(KMU)
. The
KMU is used for storing sensitive data, such as key seeds and associated
metadata, in the Secure Information Configuration Region
(SICR)
.

The SICR is divided into slots. These slots are targeted by issuing tasks to the
KMU, which can only be accessed in secure mode. Typically, application firmware
doesn’t interact with the KMU directly. Instead, PSA
drivers
are implemented
to abstract the generation, storage, and usage of keys. For example, if
invoking
psa_generate_key()
,
the operation eventually results in a call to
import_key_for_kmu()

in the CRACEN PSA
driver
.

static psa_status_t import_key_for_kmu(const psa_key_attributes_t *attributes, const uint8_t *data,
				       size_t data_length, uint8_t *key_buffer,
				       size_t key_buffer_size, size_t *key_buffer_length,
				       size_t *key_bits)
{
	size_t opaque_key_size;
	psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED;
	int slot_id =
		CRACEN_PSA_GET_KMU_SLOT(MBEDTLS_SVC_KEY_ID_GET_KEY_ID(psa_get_key_id(attributes)));
	psa_key_attributes_t stored_attributes;

	status = cracen_get_opaque_size(attributes, &opaque_key_size);
	if (status != PSA_SUCCESS) {
		return status;
	}

	if (key_buffer_size < opaque_key_size) {
		return PSA_ERROR_BUFFER_TOO_SMALL;
	}

	status = cracen_kmu_provision(attributes, slot_id, data, data_length);
	if (status != PSA_SUCCESS) {
		return status;
	}

	status = cracen_kmu_get_builtin_key(slot_id, &stored_attributes, key_buffer,
						key_buffer_size, key_buffer_length);
	if (status != PSA_SUCCESS) {
		return status;
	}

	*key_bits = psa_get_key_bits(&stored_attributes);

	return status;
}

A slot can either be erased, provisioned, or revoked. The
datasheet
includes a helpful diagram of the state machine.

debugger-lies-0

Slots have an ID (0 – 249) and can store metadata (32 bits), a destination
address (32 bits), a value (128 bits), and a revocation policy (2 bits). The
latter determines how state changes when a key is in the provisioned state and
various tasks that reference its slot ID are issued to the KMU. When
experimenting with the KMU, it is easiest to use the ROTATING revocation
policy, which dictates that the slot transitions back to the erased state when a
revoke task is issued.

When the PUSH task is issued, the value in the slot is written to the
destination address that was specified when the key was provisioned. The
provisioning process is documented in the
datasheet
,
but it can also be seen in the cracen_kmu_key_slot_provision()
implementation
:

static int cracen_kmu_key_slot_provision(const nrfx_kmu_key_slot_data_t *key_slot_data,
					 uint32_t slot_id)
{
	int kmu_status;
	uint8_t orig_write_buf_size;

	cracen_kmu_key_slot_provision_write_enable_set(true, &orig_write_buf_size);

	kmu_status = nrfx_kmu_key_slot_provision(key_slot_data, slot_id);

	cracen_kmu_key_slot_provision_write_enable_set(false, &orig_write_buf_size);
	return kmu_status;
}

The nrfx_kmu_key_slot_data_t definition can be found in the Nordic Zephyr
Hardware Abstraction Layer
(HAL)
.

typedef struct __PACKED
{
    uint32_t                     keyslot_value[KEY_SLOT_WORDS_COUNT]; ///< Key data to be provisioned.
#if NRF_KMU_HAS_REVOKE_POLICY || defined(__NRFX_DOXYGEN__)
    uint32_t                     revoke_policy;                       /**< Key revoke policy.
                                                                       *   @ref nrfx_kmu_rpolicy_t
                                                                       *   holds possible values. */
#endif
    uint32_t                     keyslot_dest;                        /**< Key slot destination when
                                                                       *   performing key push. */
#if NRF_KMU_HAS_METADATA || defined(__NRFX_DOXYGEN__)
    nrfx_kmu_key_slot_metadata_t metadata;                            ///< Metadata to write to keyslot.
#endif
} nrfx_kmu_key_slot_data_t;

You could write some fairly straightforward firmware, or even use the CRACEN
KMU
sample
,
build it, then flash it onto a development kit to easily provision a key to the
KMU. However, if using the supported drivers (which you absolutely should),
additional restrictions are placed on the values that you can use when
provisioning a key slot. For example, while the KMU supports any 32 bit value
for metadata, the PSA driver assigns
meaning

to each of the bits.

typedef struct kmu_metadata {
	uint32_t metadata_version: 4;
	uint32_t key_usage_scheme: 2;
	uint32_t reserved: 8;
	uint32_t algorithm: 6;
	uint32_t size: 3;
	uint32_t rpolicy: 2;
	uint32_t usage_flags: 7;
} kmu_metadata;

Similarly, there are restrictions on the values that you can write and the
destination to which a given type of key is pushed. If manually interacting with
the KMU, the metadata, value, and destination are much more flexible. However,
if you provision non-conformant data into slots in the KMU, then attempt to
interact with it using the supported drivers, you are going to have a bad time.

Knowing the risks, and that I could restore the SICR on nRF54LM20
DK
with
an
ERASEALL
operation on the control access port
(CTRL-AP)
,
I had powered up the board and connected with
GDB. As previously mentioned, the
KMU can only be accessed in secure mode. However, when access port protection
is not
enabled
,
the Secure Privileged Invasive Debug Enable
(SPIDEN)

signal is driven high, and the on-board J-Link debugger (J-Link
OB)
can
operate with secure privileges.

With the CPU halted, I tested that I was able to access the KMU and determined
that it was ready for operations by reading from the STATUS
register

(0x50049400).

(gdb) x/1xw 0x50049400
0x50049400:	0x00000000

To test the actual functionality, I followed the
provisioning
and
push
steps described in the datasheet. The first step was to build the SRC data
structure in memory, which is of the format specified in the packed
nrfx_kmu_key_slot_data_t struct definition. To make testing multiple values
simpler, I wrote a tiny Python script to build the struct.

import struct

open("kmu_src.bin", "wb").write(
    bytes.fromhex("abc123abc123abc123abc123abc123ab")  # Value
    + struct.pack(
        "<III",
        3,  # Revocation Policy
        0x20000000,  # Destination Address
        0xDEF678DE,  # Metadata
    )
)

The produced kmu_src.bin contained the following contents.

xxd kmu_src.bin
00000000: abc1 23ab c123 abc1 23ab c123 abc1 23ab  ..#..#..#..#..#.
00000010: 0300 0000 0000 0020 de78 f6de            ....... .x..

To write the data to memory, I used the GDB restore command.

(gdb) restore kmu_src.bin binary 0x20001000

The next step was to write the address of the struct (0x20001000) to the KMU
SRC
register

(0x50049504) and specify the desired key slot (9) in the KEY_SLOT
register

(0x50049500).

(gdb) set *(unsigned int*)(0x50049504) = 0x20001000
(gdb) set *(unsigned int*)(0x50049500) = 9

Before actually issuing the task, the resistive random access memory controller
(RRAMC)

must be configured to allow unbuffered writes. I stored the current RRAMC
CONFIG
register

(0x5004e500) in a variable to be restored after completion of the task, then
wrote the value 1, which sets write enable (WEN) field to 1 and the buffer
size (WRITEBUFSIZE) to 0 (unbuffered).

(gdb) set $rramc_config = *(unsigned int*)(0x5004e500)
(gdb) set *(unsigned int*)(0x5004e500) = 1

Finally, I wrote 1 to the TASKS_PROVISION
register

(0x50049000), instructing the KMU to store the value and its metadata in key
slot 9. I verified the event was generated by subsequently reading the
EVENTS_PROVISIONED
register

(0x50049100).

(gdb) set *(unsigned int*)(0x50049000) = 1
(gdb) x/1wx 0x50049100
0x50049100:	0x00000001

With the task completed, I then reset the RRAMC CONFIG register.

(gdb) set *(unsigned int*)(0x5004e500) = $rramc_config

These exact operations can also be seen in the CRACEN PSA
driver’s

cracen_kmu_key_slot_provision() and the underlying
nrfx_kmu_key_slot_provision()
function.

static int cracen_kmu_key_slot_provision(const nrfx_kmu_key_slot_data_t *key_slot_data,
					 uint32_t slot_id)
{
	int kmu_status;
	uint8_t orig_write_buf_size;

	cracen_kmu_key_slot_provision_write_enable_set(true, &orig_write_buf_size);

	kmu_status = nrfx_kmu_key_slot_provision(key_slot_data, slot_id);

	cracen_kmu_key_slot_provision_write_enable_set(false, &orig_write_buf_size);
	return kmu_status;
}
int nrfx_kmu_key_slot_provision(nrfx_kmu_key_slot_data_t const * p_key_slot_data, uint32_t slot_id)
{
    NRFX_ASSERT((m_cb.state == NRFX_DRV_STATE_INITIALIZED) &&
                (p_key_slot_data) &&
                (slot_id < KMU_KEYSLOTNUM));

    bool is_ready = false;

    NRFX_WAIT_FOR(nrf_kmu_status_get(NRF_KMU) == 0, 500, 10, is_ready);

    if (!is_ready)
    {
        return -EAGAIN;
    }

    nrf_kmu_src_set(NRF_KMU, (uint32_t)p_key_slot_data);
    nrf_kmu_keyslot_set(NRF_KMU, slot_id);
    nrf_kmu_task_trigger(NRF_KMU, NRF_KMU_TASK_PROVISION_KEYSLOT);

    return wait_for_task_result(NRF_KMU_EVENT_EVENTS_PROVISIONED);
}

The push operation is significantly simpler, only requiring that the desired
slot be configured in the KEY_SLOT
register
,
and the task be triggered by a write to the TASKS_PUSH
register

(0x50049004).

(gdb) set *(unsigned int*)(0x50049500) = 9
(gdb) set *(unsigned int*)(0x50049004) = 1

Similarly to the provision operation, I then checked the EVENTS_PUSHED
register

(0x50049104) to ensure the operation was successful.

(gdb) x/1wx 0x50049104
0x50049104:	0x00000001

With the EVENTS_PUSHED register indicating a successful operation, I finally
checked the destination address (0x20000000) that I had specified in the SRC
struct, which I expected to now hold the value.

(gdb) x/4wx 0x20000000
0x20000000:	0xab23c1ab	0xc1ab23c1	0x23c1ab23	0xab23c1ab

Pleased that I had successfully completed the operation, I attempted to repeat
the sequence of steps, this time using key slot 10 instead of 9, and 16
bytes of a def456 sequence instead of abc123 as the value. I issued the same
4 word read on 0x20000000 because I had reused the same destination address in
slot 10 as I had in slot 9. To my surprise the contents still matched the
previous value.

(gdb) x/4wx 0x20000000
0x20000000:	0xab23c1ab	0xc1ab23c1	0x23c1ab23	0xab23c1ab

This seemed rather peculiar, and my initial assumption was that I must have
missed a step when repeating the operation. However, no matter how many times I
attempted to push to same address (0x20000000), the value remained the same.
After erasing the device, I observed that the first push would correctly update
the value at the destination address, while subsequent pushes would not.

While astute readers may already be smelling a stale cache, it is worth taking a
step back and examining the debug architecture of the nRF54LM20. Like most Arm
systems, it implements to the Arm Debug Interface
(ADI)
, specifically leveraging
the Arm CoreSight SoC-400
implementation. It has three access ports: two standard
AHB-AP
and one custom CTRL-AP. The first AHB-AP is used to communicate with the main
Cortex-M33 CPU, while the latter is used for accessing auxiliary units,
specifically the RISC-V VPR
coprocessor
. The
aforementioned CTRL-AP enables a small subset of functionality that is typically
leveraged in a scenario in which the AHB-APs have been disabled (i.e. access
port protection is enabled).

debugger-lies-1

In order for GDB to interact with the J-Link OB, it needs something to translate
between the commands it supports and those supported by the underlying debugger.
JLinkGDBServer
plays that role when working with J-Link debuggers. GDB effectively acts as a
consistent interface to heterogeneous backends, so when you want to read the
contents of a given memory address, you can use the same command whether you are
debugging a microcontroller or a process on your local development machine.

You can also issue commands directly to the GDB server implementation using the
the GDB monitor command. For example, JLinkGDBServer supports a ReadMemAP
command
, which allows you to
directly specify the access port to target, the memory address, the number of
items, and a set of flags. Suspecting that my push operations may be succeeding,
but my reads returning stale values, I issued a ReadMemAP command with the
same parameters as my GDB memory read commands.

(gdb) monitor ReadMemAP 0x0 0x20000000 4 0
O.K.:0xDE56F4DE,0xF4DE56F4,0x56F4DE56,0xDE56F4DE

Sure enough, reading directly from the AHB-AP showed the expected value.
Furthermore, after issuing the read, subsequent examine (x) commands from GDB
continued to return stale values. GDB and JLinkGDBServer communicate using the
GDB Remote Serial Protocol
(RSP)
,
and the specific packets transmitted between them can be observed by enabling
remote debug logging.

(gdb) set debug remote 1

Given the observed behavior, I suspected that the two different memory read
strategies used different RSP packets. This was confirmed after issuing commands
with the debug logging enabled.

(gdb) x/4wx 0x20000000
[remote] Packet received: b??}03?
0xab23c1ab	[remote] Sending packet: $x20000004,4#5e
[remote] Packet received: b?}03??
0xc1ab23c1	[remote] Sending packet: $x20000008,4#62
[remote] Packet received: b}03??}03
0x23c1ab23	[remote] Sending packet: $x2000000c,4#8d
[remote] Packet received: b??}03?
0xab23c1ab
(gdb) monitor ReadMemAP 0x0 0x20000000 4 0
[remote] Sending packet: $qRcmd,526561644d656d415020307830203078323030303030303020342030#a0
[remote] Packet received: 4f2e4b2e3a307844453536463444452c307846344445353646342c307835364634444535362c307844453536463444450D0A
O.K.:0xDE56F4DE,0xF4DE56F4,0x56F4DE56,0xDE56F4DE

In fact, the ReadMemAP command is passed hex encoded directly to
JLinkGDBServer using a qRcmd (remote command query) packet.

echo 526561644d656d415020307830203078323030303030303020312030 | xxd -r -p
ReadMemAP 0x0 0x20000000 4 0

The question of why JLinkGDBServer opted to return stale values for one read
and not the other remained. Though the documentation on JLinkArm.dll, the
underlying library that most J-Link tooling depends on, is fairly light, there
is a list of supported command
strings
that gives a clue as to
its internal caching behavior. Specifically, the SetEnableMemCache
command
is
defined as controlling memory caching mechanisms, and is on by default. There is
even a somewhat ominous note about turning it off.

This command may not be used by any IDE, listed as a supported IDE, to disable
memory cache mechanisms by default. It may only be used by specific customers
for very specific test cases that needs the cache mechanisms to be disabled.

Eager to observe if disabling the memory cache actually resulted in fresh values
being returned when issuing examine commands, I once again erased the device and
connected GDB. Before performing any operations, I disabled the memory cache.

(gdb) monitor exec SetEnableMemCache = 0

Running through the provision and push operations for the first slot, I observed
the expected value as before. Then on the second provision and push, the examine
command finally returned the updated value.

(gdb) x/4wx 0x20000000
0x20000000:	0xde56f4de	0xf4de56f4	0x56f4de56	0xde56f4de

However, as the J-Link documentations states, you typically do not want to turn
off caching. The reason why the JLinkArm.dll memory cache returns stale values
in this case is because the CPU is halted and we are attempting to read from a
memory address that we have already accessed without advancing the CPU. With the
memory cache enabled, advancing the CPU a few instructions (stepi) results in
the cache being cleared and a fresh value being returned on the next read.

Outside of use cases where a peripheral, such as the nRF54LM20’s KMU, has
direct memory access (DMA)
and can write while the core is halted, you typically won’t encounter issues
with stale debugger memory cache values. In the event that you do, it can be
helpful to understand the underlying bus architecture and how to bypass the
cache by reading directly from an access port.


Source: Hacker News

The "Windows XP Box" (2003)

July 15, 2024KUBIC is a Nintendo-themed, 3D Printable Mini-ITX case

September 05, 2017Choosing the right DC-DC PSU

August 27, 2015AMD's Project Quantum

August 13, 2015The Redstone PC is the ultimate Mini-ITX Minecraft Machine

October 09, 2014The "Restomod TV"

April 09, 2013Installing NAS4Free

February 28, 2013Building an XBMC 12 Home Theatre PC

January 25, 2011XBMC Guide updated to version 10.0

August 06, 2010Building a Green PC

February 15, 2010Building an ION powered HTPC with XBMC

October 10, 2008The "Cambridge Autonomous Underwater Vehicle 2008"

September 12, 2008"Florian", the DVD burning robot

September 05, 2008The "i-EPIA"

January 19, 2007The "ITX-Laptop"

December 07, 2006The "Tortoise Beetle"

October 02, 2006The "DOS Head Unit"

August 31, 2006The "Janus Project"

June 26, 2006Nano-ITX in a Football

May 17, 2006The "EPIA Alloy Mod"

April 11, 2006Neatorama's Collection of Case Mods

February 18, 2006The "Rundfunker"

August 05, 2005The "Waffle Iron PC"

July 21, 2005The "Supra-Server"

July 07, 2005The "Encyclomedia"

May 25, 2005The "Accordion ITX"

May 16, 2005The "FileServerRouterSwitch"

January 30, 2005First Nano-ITX Project?

January 15, 2005The "Gumball PC"

December 15, 2004The "Deco Box"

December 03, 2004The "TERA-ITX"

October 06, 2004The "Coealacanth-PC"

September 17, 2004The "Gramaphone-ITX-HD"

August 26, 2004The "C1541 Disk Drive ITX"

August 13, 2004The "Quiet Cubid"

July 14, 2004The "Moo Cow Moo"

Full alphabetical archive on right hand side of page…

I needed a small Windows XP machine and a Mini-ITX board was the obvious choice. So I decided to build my "Windows XP Box" in a Windows XP box. The external dimensions of the box are a tiny 243mm x 200mm x 48mm.

 Fortunately there is no longer any requirement for an internal floppy drive. That would have have defeated me.

The bits arrive and it looks like an impossible task, with too many bits to fit in a small space.

I nearly gave up and decided it was an impossible task. The Windows XP box was 3mm thinner and 12 mm narrower than the Adobe Acrobat box I had measured up when first deciding if the project was going to be possible. The challenge was to arrange the components into a 3D jigsaw, then decide how to build enough of an internal support case to get everything to stay in place.

Eventually it looked like I might have a possible layout, but the tolerances were tight. I had 6mm to spare on the long internal dimension of the box and only 3mm to spare on the thickness of the box, and this was not allowing for any thickness for the internal support case that holds everything in place.

In order to mount all the bits I was going to have to make an inner support case that would tightly slide into the cardboard box. I chose Wonderboard plastic as my construction material because it is reasonably strong and very easy to work with (it cuts with a Stanley knife). It would have been nice to use aluminium, but the cramped design made the chances of a short circuit too great.

The first construction step was to cut out a base plate the exact size of the inside of the cardboard box and double check where the bits will fit.

As the Wonderboard was 3mm thick this reduced my tolerance in two dimensions to zero. The CD drive would touch one side of the inner support case. The deep part of the CD drive would touch the heat sink on the motherboard, with the narrow bit being able to overlap it, and the far side of the motherboard touches the other side of the Wonderboard case. In the other dimension it was even harder. The top of the sound connector would touch the support case, and the underside of the motherboard would touch the cardboard box. Fortunately the hard drive can slide under the motherboard as this is above (below?) the unused PCI slot. The only place left for the PSU was above the hard drive with the bulky connectors facing down towards the CD both to the front and the back of the hard drive.

Now I could position the CD drive hard against the side and start assembling the support case. In the next picture you can see the step up between the thin part of the CD drive and the thicker part of the main body of the drive. The heat sink on the Mini-ITX board touches this step.

After much cutting and half a tube of glue the case was finished. I built pillars to support three corners of the motherboard and the power supply and added brackets to support the CD and the hard drive. In such a compact design cooling was a concern so I made fan mounting points in opposite corners of the case. To keep the CPU nice and cool I cut a hole for it it the side of the case and glued in a couple of plates to act as ducting so the CPU fan will only suck in cold outside air. The other two fans are the exhaust points. The fan guards were cut out of a metal speaker grill using an angle grinder as neatly drilling that many holes is just not fun. Angle grinders are almost as much fun to use as chain saws.

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Enjoy Every Sandwich


Source: Hacker News

RAM: the forgotten history (2024)


Source: Hacker News

Coulomb's law remains tricky to test at home


Source: Hacker News

Web-based IBM 1620 emulator and IPL-V from 1963

retro-1620

Web-based emulator and operating environment for the IBM 1620 Model-2 computer system.

The IBM 1620 was a 1960s transistorized, decimal, variable field-length, magnetic-core memory computer system designed primarily as an inexpensive solution for scientific and engineering applications. There were two models, the original Model 1 released in 1959, and the object-code compatible but significantly redesigned Model 2, released in 1962. A total of about 2,000 systems were produced, roughly half each Model-1s and Model-2s. IBM supported the system until 1970.

The 1620 used a two-address, memory-to-memory architecture. There were no software-accessible registers. Instructions were a fixed 12 digits, consisting of an operation code of two digits, a “P” address of five digits (usually the destination operand), and a “Q” address or literal value of five digits (usually the source operand). The basic memory size was 20,000 digits, expandable to 60,000 digits. Each digit contained a four-bit binary-coded decimal value, a fifth “flag” bit used for both the arithmetic sign and as a field delimiter, and an odd-parity “check” bit. All arithmetic and data movement was done digit-sequentially.

  • The Model 1 featured a memory cycle time of 20µs per two digits. Addition and multiplication were done via a lookup table in memory. Hardware division, floating-point arithmetic, and indirect addressing were optional features.

  • The Model 2 featured a memory cycle time of 10µs per two digits. Many instructions were optimized to process two Q-operand digits from a single memory fetch. Addition was done in hardware, but multiplication was still done by table lookup. Hardware division and indirect addressing were standard features, with floating-point still an extra-cost option. The Model 2 had two additional options, index register address modification (with the index registers stored in memory at 00300-00399, where the Model 1 add table had resided) and support for binary (actually, octal) bit-wise operations, octal/decimal conversion, and binary paper tape I/O.

Initially, the Model 1 supported only paper-tape and typewriter input/output devices, but the 1622 card reader/punch unit (derived from the IBM 1401’s model 1402 reader/punch) was made available soon after the initial release. Additional peripherals were the 1443 line printer, 1311 disk drive with removable disk packs, and 1627 plotter. The typewriter, paper tape, punched card, and printer devices supported alphanumeric data in memory as pairs of adjacent digits.

The 1620 was also used as the computing and control component of the IBM 1710 and 1720 process-control systems. When configured for this role, the 1620 supported several additional instructions and a multi-level interrupt system.

The 1620 had a vast collection of IBM-supplied and user-written software. Most programming was done using the SPS assembler or FORTRAN II. For systems with the 1311 disk drive, there was a simple batch operating system known as “Monitor.”

The main goals of this project are creation of a web browser-based emulator for the Model 2 variant of the system and recovery of as much software for the system as we are able to find.

The contents of this project are licensed under the MIT License.

Related Sites URL
Emulator hosting site http://www.phkimpel.us/IBM-1620/
Project Wiki https://github.com/pkimpel/retro-1620/wiki/
Project Blog https://retro-emulation.blogspot.com/
1620 Documents at bitsavers http://bitsavers.org/pdf/ibm/1620/
1620 Software at bitsavers http://www.bitsavers.org/bits/IBM/1620/
1620 Wikipedia page https://en.wikipedia.org/wiki/IBM_1620

Source: Hacker News